The present application claims priority under 35 U.S.C. xc2xa7119 to Korean Application No. 2000-65258 filed on Nov. 3, 2000, which is hereby incorporated by reference in its entirety for all purposes.
1. Field of the Invention
The present invention relates to a semiconductor device with metal interconnection and a method for forming metal interconnections of a semiconductor device, and more particularly, to a semiconductor device with double damascene metal interconnections and a method for forming the metal interconnections of a semiconductor device.
2. Description of the Related Art
With the increase in integration density of semiconductor devices, conductive layers for a semiconductor device have been deposited on a wafer with a multi-level structure. The multi-level interconnection structure contributes to reducing the cell area and design rule of the semiconductor device, thereby increasing the integration density of the semiconductor device. For multi-level interconnections having smaller size, it would be desirable to conduct extensive research and development into advanced metal interconnection structures and alternative materials used to form interconnections.
A double damascene technique has been used to form advanced interconnections. According to the double damascene technique, a trench aligned with a gate electrode and a via hole through which a selected junction area is exposed are formed, and both the trench and the via hole are filled with a conductive material by the same process. Thus, the double damascene technique is advantageous because it simplifies the entire metal interconnection process.
A structure of metal interconnection of a semiconductor device manufactured using a conventional double damascene technique is shown in FIG. 1. FIG. 2 is a plan view of the metal interconnection shown in FIG. 2. Referring to FIGS. 1 and 2, a gate insulating layer 21 and a conductive layer for forming a gate electrode is deposited in succession on a semiconductor substrate 20 having a first conductive type. A selected portion of the conductive layer is patterned into a gate electrode 23. Spacers 25 are formed on the sidewalls of the gate electrode 23 by a known technique. Impurities having a second conductive type, which is an opposite type to that of the semiconductor substrate 20, are implanted into substrate 20 on both sides of the gate electrode 23, thereby forming junction area 27.
A first interlevel dielectric (ILD) film 29 is formed over the semiconductor substrate 20 having the gate electrode 23 and the junction area 27, to a thickness of 8,000-20,000 xc3x85. Following this, the surface of the first ILD film 29 is polished a predetermined depth by chemical mechanical polishing. A selected portion of the first ILD film 29 is patterned to form a trench T aligned with the gate electrode 23, and a via hole H through which the junction area 27 between adjacent gate electrodes is exposed. Here, a selected portion of the first IDL film 29 is removed by etching to form the trench T, such that the depth of the trench T is smaller than the depth of the via hole H.
Following this, an adhesive layer 31 is deposited along the surface of the first ILD film 29 and in the via hole H and the trench T, and a metal layer 32 is thereafter deposited on the structure to fill the via hole H and the trench T. The metal layer 32 and the adhesive layer 31 are polished by chemical mechanical polishing until the surface of the first ILD film 29 is exposed. As a result, first metal interconnections 34a and 34b having the metal layer 32 and the adhesive layer 31 embedded in the via hole H and the trench T are completed. In this case, since the first metal interconnection 34b formed in the trench T are aligned with the gate electrode 23, a series of first metal interconnections 34b are arranged in lines parallel to each other over the substrate 20, separated by a predetermined distance from each other, as shown in FIG. 2.
Next, a second ILD film 36 is deposited over the first ILD film 29 including the first metal interconnections 34a and 34b therein, and then the second ILD film 36 is partially etched such that the first metal interconnection 34a filling the via hole H is exposed. A second metal interconnection 38 is formed over the second ILD film 29 such that the second metal interconnection 38 contacts the first metal interconnection 34a, which is exposed by etching. The second metal interconnection 38 is formed to be perpendicular to the first metal interconnection 34b filling the trench T, as shown in FIG. 2.
However, there are problems in forming metal interconnections by the conventional double damascene technique. Chemical mechanical polishing causes aggregations of slurry that is applied as an abrasive, and polishing residues, (not shown) to remain on the polished surface of a layer. As a result, when physical force is applied through a polishing pad to polish the first ILD film 29 for example, the surface of the first ILD film 29 is scratched due to the presence of such slurry aggregations and polishing residues. Scratches on the surface of the first ILD film 29, which are caused by the slurry aggregations and polishing residues, are referred to as xe2x80x9cmicroscratchesxe2x80x9d. As shown in FIG. 2, microscratches 39 occur in lines in a polishing direction. The depth of the microscratches 39 vary depending on the force applied to the polishing pad and the particle size of the slurry aggregates and polishing residues. Usually, the depth of the microscratches 39 are in the range of 500-1500 xc3x85, but if serious, can be as deep as 2000 xc3x85.
During formation of the first metal interconnections 34a and 34b, portions of the adhesive layer 31 and the metal layer 32 remain caught in the unnecessary microscratches formed on the first ILD film 29. As shown in FIG. 2, since the microscratches 39 occur in lines along a polishing direction, the remaining metal layer 32 serves as bridges between adjacent first metal interconnections 34a and 34b, as shown in FIGS. 3 and 4, thereby causing a short between the first metal interconnections 34a and 34b. As a result, failure occurs during the manufacture of semiconductor devices, thereby degrading the electrical properties of semiconductor devices.
The present invention is therefore directed to a semiconductor device with improved metal interconnection, and a method of forming the metal interconnection, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.
To solve the above problems, it is a first object of the present invention to provide a semiconductor device with improved metal interconnections, which does not include shorts between adjacent metal interconnections.
It is a second object of the present invention to provide a method for forming metal interconnections of a semiconductor device, which is capable of preventing the occurrence of shorts between the metal interconnections formed using a double damascene technique.
The first and other objects of the present invention are achieved by a semiconductor device with an improved metal interconnection structure, including a substrate in which a plurality of conductive areas are defined, and an interlevel dielectric (ILD) film with a polished surface that covers the substrate and that has a via hole and a trench with a smaller depth than the via hole. Here, a selected conductive area is exposed through the via hole. The semiconductor device also includes a metal interconnection formed in each of the via hole and the trench, and an anti-short insulating layer formed on the sidewalls of the metal interconnection formed in the trench.
The anti-short insulating layer may be further formed on the bottom of the trench filled with the metal interconnection, and on the surface of the ILD film adjacent to the trench. The anti-short insulating layer may be formed of the same insulating layer as the ILD film, or an insulating layer having a polishing selectivity of 15:1 or greater with respect to the metal interconnection, such as a silicon nitride layer or a silicon oxynitride layer. Also, the metal interconnection may comprise a metal layer formed in the trench and in the via hole, and an adhesive layer interposed between the metal layer and the ILD film.
In another embodiment, there is provided a semiconductor device with an improved metal interconnection structure, including a substrate in which a plurality of conductive areas are defined, and an interlevel dielectric (ILD) film with a polished surface that covers the substrate and that has a via hole and a trench with a smaller depth than the via hole. Here, a selected conductive area is exposed through the via hole. The semiconductor device also includes a metal interconnection formed in each of the via hole and the trench, and an insulating spacer formed on the sidewalls of the metal interconnection formed in the trench.
The semiconductor device may further include a polishing stop layer formed on the surface of the ILD film adjacent to the trench, on the insulating spacer in the trench, and on the bottom of the trench. The polishing stop layer and the spacer may be formed of the same insulating layer. Alternatively, the polishing stop layer and the spacer may be formed of the same insulating layer as the ILD film, or the spacer may be formed of an insulating layer having a polishing selectivity of 15:1 or greater with respect to the metal interconnection.
To achieve the second and other objects of the present invention, there is provided a method for forming a metal interconnection of a semiconductor device, the method comprising preparing a semiconductor substrate in which a plurality of conductive areas are defined. An interlevel dielectric (ILD) film with a polished surface is formed over the semiconductor substrate. Next, a portion of the ILD film, below which a conductive area selected from the plurality of the conductive areas is not located, is etched a predetermined depth to form a trench. An anti-short insulating layer is formed on the ILD film and in the trench. Then, the anti-short insulating layer and the ILD film are etched to form a via hole through which the selected conductive area is exposed. Lastly, the trench and the via hole are filled with metal to form a metal interconnection.
In another embodiment, there is provided a method for forming a metal interconnection of a semiconductor device, the method comprising preparing a semiconductor substrate in which a plurality of conductive areas are defined. An interlevel dielectric (ILD) film with a polished surface is formed over the semiconductor substrate. Then, a portion of the ILD film, below which a conductive area selected from the plurality of the conductive areas is not located, is etched by a predetermined depth to form a trench. An anti-short insulating layer is formed on the ILD film and in the trench. Following this, the anti-short insulating layer is etched back such that the ILD film is exposed while the anti-short insulating layer remains as spacers only on both sidewalls of the trench. A portion of the ILD film is etched to form a via hole through which the selected conductive area is exposed. Lastly, the trench and the via hole are filled with metal to form a metal interconnection.
Forming the metal interconnection may comprise forming an adhesive layer along the ILD film and in the trench and the via hole; forming a metal layer over the adhesive layer such that the trench and the via hole are completely filled; and polishing the metal layer and the adhesive layer until the surface of the metal ILD film is exposed.
After the formation of the spacers and before the formation of the via hole, the method may further include forming a polishing stop layer over the ILD film and the spacers. In this way, the polishing stop layer may be formed of the same insulating layer as the anti-short insulating layer. For example, the anti-short insulating layer and the polishing stop layer can be formed of the same material layer as the ILD film, or an insulating layer having a polishing selectivity of 15:1 or greater with respect to the metal interconnection.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.